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general description the max5953a/max5953b/max5953c/max5953dintegrate a complete power ic solution for powered devices (pd) in a power-over-ethernet (poe) system, in compliance with the ieee 802.3af standard. the max5953a/max5953b/max5953c/max5953d provide the pd with a detection signature, a classification sig- nature, and an integrated isolation switch with program- mable inrush current control. these devices also integrate a voltage-mode pwm controller with two power mosfets connected in a two-switch voltage- clamped dc-dc converter configuration. an integrated mosfet provides pd isolation during detection and classification. all devices guarantee a leakage current offset of less than 10? during the detection phase. a programmable current limit pre- vents high inrush current during power-on. the devices feature power-mode undervoltage lockout (uvlo) with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. the max5953a/max5953c have an adjustable uvlo threshold with the default value compliant to the 802.3af standard, while the max5953b/max5953d have a lower and fixed uvlo threshold compatible with some legacy pre-802.3af power-sourcing equipment (pse) devices. the dc-dc converters are operable in either forward or flyback configurations with a wide input voltage range from 11v to 76v and up to 15w of output power. the voltage-clamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. when using the high-side mosfet, the controller can be configured as a buck converter. a look-ahead signal for driving sec- ondary-side synchronous rectifiers can be used to increase efficiency. a wide array of protection features include uvlo, over-temperature shutdown, and short- circuit protection with hiccup current limit for enhanced performance and reliability. operation up to 500khz allows for smaller external magnetics and capacitors. the max5953a/max5953b/max5953c/max5953d are available in a high-power (2.22w), 7mm x 7mm ther- mally enhanced thin qfn package. features ? powered device interface fully integrated ieee 802.3af-compliant pd interface pd detection and programmable classification signatures less than 10a leakage current offset during detection integrated mosfet for isolation and inrush current limiting gate output allows external control of the internal isolation mosfet programmable inrush current controlprogrammable undervoltage lockout (max5953a/max5953c) ? dc-dc converter clamped, two-switch power ic for high efficiency integrated high-voltage 0.4 ? power mosfets up to 15w output power bias voltage regulator with automatic high- voltage supply turn-off 11v to 76v wide input voltage rangefeed-forward voltage-mode control for fast input transient rejection programmable undervoltage lockoutovertemperature shutdown indefinite short-circuit protection with programmable fault integration integrated look-ahead signal for secondary- side synchronous rectification > 90% efficiency with synchronous rectification up to 500khz switching frequency ? high-power (2.22w), 7mm x 7mm thermallyenhanced lead-free thin qfn package max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ________________________________________________________________ maxim integrated products 1 part pin-package pkg code max5953a utm+ 48 tqfn t4877-6 max5953b utm+ 48 tqfn t4877-6 max5953c utm+ 48 tqfn t4877-6 max5953d utm+ 48 tqfn t4877-6 ordering information 19-3945; rev 1; 7/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. operating junction temperature range is 0? to +125?. + denotes lead-free package. pin configuration and typical operating circuit appear atend of data sheet. ieee 802.3af powereddevices ip phones wireless access nodes internet appliancessecurity cameras computer telephony applications downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v in = (v+ - v ee ) = 48v, gate = pgood = pgood = unconnected, gnd = out, hvin = v+, uvlo = v ee , t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25?. all voltages are referenced to v ee , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to v ee ................................................................-0.3v to +90v out, pgood, pgood to v ee .....................-0.3v to (v+ + 0.3v) rclass, gate to v ee ...........................................-0.3v to +12v uvlo to v ee ............................................................ -0.3v to +8v pgood to out ........................................... -0.3v to (v+ + 0.3v) hvin, inbias, drnh, xfrmrh, xfrmrl to gnd.................................................-0.3v to +80v bst to gnd ........................................................... -0.3v to +95v bst to xfrmrh .................................................... -0.3v to +12v pgnd to gnd .......................................................-0.3v to +0.3v dcuvlo, ramp, css, opto, fltint, rcff, rtct to gnd..................................................... -0.3v to +12v src, cs to gnd...................................................... -0.3v to +6v regout, drvin to gnd .......................................-0.3v to +12v regout to hvin .................................................. -80v to +0.3v regout to inbias ............................................... -80v to +0.3v ppwm to gnd....................................-0.3v to (v regout + 0.3v) maximum input/output current (continuous) out to v ee ....................................................................500ma v+, rclass to v ee .........................................................70ma uvlo, pgood, pgood to v ee .....................................20ma gate to v ee ....................................................................80ma regout to gnd ............................................................50ma drnh, xfrmrh, xfrmrl, src to gnd (average), t j = +125?..................................................................0.9a ppwm to gnd ..............................................................?0ma continuous power dissipation* (t a = +70?) 48-pin tqfn 7mm x 7mm (derate 27.8mw/? above +70?) .............................2222mw ja ................................................................................36?/w operating ambient temperature range ................0? to +85? operating junction temperature range ..............0? to +125? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units powered device (pd) interface detection mode input offset current i offset v in = 1.4v to 10.1v (note 2) 10 ? effective differential inputresistance (note 3) dr v in = 1.4v, up to 10.1v with 1v step 550 k ? classification mode classification current turn-offthreshold v th , class v in rising (note 4) 20.8 21.8 22.5 v class 0, r rclass = 10k ? 02 class 1, r rclass = 732 ? 9.17 11.83 class 2, r rclass = 392 ? 17.29 19.71 class 3, r rclass = 255 ? 26.45 29.55 classification current i class v in = 12.6v to 20v,r disc = 25.5k ? (notes 5, 6) class 4, r rclass = 178 ? 36.6 41.4 ma power mode operating supply voltage v in v in = (v+ - v ee )6 7 v operating supply current i in measure at v+, not including r disc , gate = v ee , hvin = gnd = out 0.4 1 ma max5953a/max5953c 37.4 38.6 40.2 default power turn-on voltage v uvlo , on v in increasing max5953b/max5953d 34.3 35.4 36.9 v default power turn-off voltage v uvlo , off v in decreasing, max5953a/max5953c 30 v *as per jedec 51 standard. downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets _______________________________________________________________________________________ 3 electrical characteristics (continued)(v in = (v+ - v ee ) = 48v, gate = pgood = pgood = unconnected, gnd = out, hvin = v+, uvlo = v ee , t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25?. all voltages are referenced to v ee , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units max5953a/max5953c 7.1 default power turn-on/offhysteresis voltage v hyst , uvlo max5953b/max5953d 4 v external uvlo programmingrange v in,ex max5953a/max5953c only (note 7) 12 67 v uvlo external referencevoltage v ref , uvlo v uvlo increasing 2.400 2.460 2.522 v uvlo external referencevoltage hysteresis v hyst , uvlo ratio to v ref, uvlo 19.2 20 20.9 % uvlo bias current i in,uvlo v uvlo = 2.460v -1.5 +1.5 ? uvlo input ground-sensethreshold v th , g , uvlo (note 8) 50 440 mv uvlo input ground-sense glitchrejection 7 s power turn-off voltage,undervoltage lockout deglitch time t off_dly v in , v uvlo falling (note 9) 0.32 ms isolation switch n-channelmosfet on-resistance r on,iso output current = 300ma, v gate = 5.6v, measured between out and v ee 0.6 1.5 ? isolation switch n-channelmosfet off-threshold voltage v gsth v gate - v ee , out = v+, output current < 1? 0.5 v gate pulldown switchresistance r g power-off mode, v in = +12v 38 80 ? gate charging current i gate v gate = 2v 4.5 10 16.5 ? gate high voltage v gate i gate = 1? 5.59 5.76 5.93 v v out - v ee decreasing, v gate = 5.75v 1.16 1.23 1.31 v pgood assertion v out threshold (note 10) v outen hysteresis 70 mv v gate - v ee increasing 4.62 4.76 4.91 v pgood, pgood assertion v gate threshold v gsen hysteresis 80 mv pgood, pgood output low voltage v ol , pgood i sink = 2ma, v out (v+ - 5v) (note 11) 0.2 v pgood leakage current gate = high, v+ - v out = 67v (note 11) 1 a pgood leakage current gate = v ee , pgood - v ee = 67v (note 11) 1 a downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 4 _______________________________________________________________________________________ electrical characteristics (dc-dc controller)(all voltages referenced to gnd, unless otherwise noted. v hvin = +48v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v dcuvlo = 3v, t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input supply range v hvin 11 76 v oscillator (rtct) pwm frequency f s 250 khz maximum pwm duty cycle d max 47 % maximum rtct frequency f rtctmax (note 12) 1 mhz rtct peak trip level v th,rtct 0.51 x v regout v rtct valley trip level v tl,rtct 1v rtct input bias current i in,rtct ? ? rtct discharge mosfetr ds(on) r dis,rtct sinking 50ma 35 85 ? rtct discharge pulse width 50 ns look-ahead logic (ppwm) ppwm to output propagationdelay t ppwm v ppwm rising to v xfrmrl falling 110 ns ppwm output high v oh,ppwm sourcing 2ma 7.0 11.0 v ppwm output low v ol,ppwm sinking 2ma 0.2 v pwm comparator (opto, ramp, rcff) common-mode input range v cm_pwm 0 5.5 v input offset voltage 10 mv input bias current -2 +2 ? ramp to xfrmrl propagationdelay t comparator from v ramp (50mv overdrive) rising to v xfrmrl rising 100 ns minimum opto voltage v css = 0v, opto sinking 2ma 1.47 v minimum rcff voltage rcff sinking 2ma 2.18 v regout ldo (regout) inbias unconnected,v hvin = 11v to 76v 8.3 8.75 9.2 regout voltage set point v regout v inbias = v hvin = 11v to 76v 9.5 10.6 11.0 v inbias unconnected, v hvin = 15v, i regout = 0 to 30ma 0.25 regout load regulation v inbias = v hvin = 15v, i regout = 0 to 30ma 0.25 v inbias unconnected, i regout = 30ma 1.25 regout dropout voltage v inbias = v hvin , i regout = 30ma 1.25 v regout undervoltagelockout threshold regout rising 6.6 7.0 7.4 v regout undervoltage lockout threshold hysteresis regout falling 0.7 v downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets _______________________________________________________________________________________ 5 electrical characteristics (dc-dc controller) (continued)(all voltages referenced to gnd, unless otherwise noted. v hvin = +48v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v dcuvlo = 3v, t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units soft-start (css) soft-start current i css v css = 0v 33 ? integrating fault protection fltint source current i fltint 80 ? fltint trip point v fltint rising 2.7 v fltint hysteresis 0.75 v internal power fets on-resistance r on , power v drvin = v bst = 9v, v xfrmrh = v src = 0v, i ds = 50ma 0.4 0.8 ? off-state leakage current -5 +10 ? total gate charge per powerfet 15 nc high-side driver low to high latency t lh-hs driver delay until fet v gs reaches 0.9 x (v bst - v xfrmrh ) and is fully on 80 ns high to low latency t hl-hs driver delay until fet v gs reaches 0.1 x (v bst - v xfrmrh ) and is fully off 40 ns output drive voltage v bst bst to xfrmrh with high side on 8 v low-side driver low to high latency t lh-ls driver delay until fet v gs reaches 0.9 x v drvin and is fully on 80 ns high to low latency t hl-ls driver delay until fet v gs reaches 0.1 x v drvin and is fully off 40 ns current-limit comparator (cs) current-limit thresholdvoltage v ilim 140 156 172 mv current-limit input biascurrent i bilim 0 < v cs < 0.3v -2 +2 ? propagation delay to xfrmrl t dilim from v cs rising (10mv overdrive) to v xfrmrl rising 160 ns boost voltage circuit (see figure 9, qb) driver output delay t ppwmd 200 ns one-shot pulse width t pwqb 300 ns qb r dson sinking 20ma 30 60 ? thermal shutdown shutdown temperature t sh temperature rising +160 ? thermal hysteresis t h 20 ? downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 6 _______________________________________________________________________________________ electrical characteristics (dc-dc controller) (continued)(all voltages referenced to gnd, unless otherwise noted. v hvin = +48v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v dcuvlo = 3v, t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units undervoltage lockout (dcuvlo) threshold voltage v ref , dcuvlo v dcuvlo rising 1.14 1.26 1.38 v hysteresis v hys , dcuvlo 140 mv input bias current i in,dcuvlo v dcuvlo = 3v -100 +100 na supply current from v hvin = 11v to 76v, v css = 0v, v inbias = 11v 0.7 1.5 from v inbias = 11v to 76v, v css = 0v, v hvin = 76v 4.4 6.4 supply current from v hvin = 76v, v opio = 4v 7 ma standby supply current v dcuvlo = 0v 1 ma note 1: limits at 0? are guaranteed by design, unless otherwise noted. note 2: the input offset current is illustrated in figure 1. note 3: effective differential input resistance is defined as the differential resistance between v+ and v ee without any external resistance. note 4: classification current is turned off whenever the ic is in power mode. note 5: see table 2 in the classification mode section. r disc and r rclass must be 1%, 100ppm or better. i class includes the ic bias current and the current drawn by r disc . note 6: see the thermal dissipation section. note 7: when uvlo is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k ? (?%), the turn- on threshold set point for the power mode is defined by the external resistor-divider. make sure the voltage on uvlo doesnot exceed its maximum rating of 8v when v in is at the maximum voltage. note 8: when v uvlo is below v th,g,uvlo , the max5953a/max5953c set the turn-on voltage threshold internally (v uvlo,on ). note 9: an input voltage or v uvlo glitch below their respective thresholds shorter than or equal to t off_dly does not cause the max5953a/max5953b/max5953c/max5953d to exit power-on mode (as long as the input voltage remains above anoperable voltage level of 12v). note 10: guaranteed by design, not tested in production for max5953b/max5953d. note 11: pgood references to out while pgood references to v ee . note 12: output switching frequency is 1 / 2 oscillator frequency. figure 1. effective differential input resistance/offset current i in i ini + 1 i ini i offset dr i 1v v ini v ini + 1 i offset ? i ini - v ini dr i dr i ? (v ini + 1 - v ini ) = 1v (i ini + 1 - i ini ) (i ini + 1 - i ini ) v in downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets _______________________________________________________________________________________ 7 detection current vs. input voltage max5953a/b/c/d toc01 input voltage (v) detection current (ma) 8 6 4 2 0.1 0.2 0.3 0.4 0.5 0 01 0 r disc = 25.5k ? i in + i rdisc classification current vs. input voltage max5953a/b/c/d toc02 input voltage (v) classification current (ma) 25 20 15 10 5 5 10 15 20 25 30 35 40 45 50 0 03 0 class 4 class 3 class 2 class 1 class 0 effective differential input resistance vs. input current max5953a/b/c/d toc03 input voltage (v) effective differential input resistance (m ? ) 8 6 4 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 01 0 input offset current vs. input voltage max5953a/b/c/d toc04 input voltage (v) input offset current ( a) 8 6 2 4 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -4.0 01 0 normalized uvlo vs. temperature max5953a/b/c/d toc05 temperature ( c) normalized uvlo 100 75 50 25 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.0100.990 01 2 5 pgood output low voltage vs. current max5953a/b/c/d toc06 i sink (ma) v pgood (mv) 15 10 5 50 100 150 200 250 0 02 0 out leakage current vs. temperature max5953a/b/c/d toc07 temperature ( c) out leakage current (na) 100 75 50 25 1 10 100 1000 0.1 01 2 5 v out = 48v inrush current control (v in = 48v) max5953a/b/c/d toc08 4ms/div v out to v ee 50v/div v gate 5v/div 0v0v 0a 0v i inrush 100ma/div pgood 50v/div dcuvlo threshold vs. temperature max5953a/b/c/d toc09 temperature ( c) v dcuvlo (v) 100 75 50 25 1.2750 1.2775 1.2800 1.28251.2725 0 125 dcuvlo rising typical operating characteristics (v in = (v+ - v ee ) = 48v, gate = pgood = unconnected, gnd connected to out, hvin connected to v+, uvlo = v ee , c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25?. all voltages are referenced to v ee , unless otherwise noted.) downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v in = (v+ - v ee ) = 48v, gate = pgood = unconnected, gnd connected to out, hvin connected to v+, uvlo = v ee , c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25?. all voltages are referenced to v ee , unless otherwise noted.) hvin standby current vs. temperature max5953a/b/c/d toc10 temperature ( c) standby current ( a) 100 75 50 25 35 70 105 140 175 210 245 280 315 350 385 0 0 125 f hvin v dcuvlo = 0v hvin input current vs. temperature max5953a/b/c/d toc11 temperature ( c) i hvin (ma) 100 75 25 50 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.84.0 0 125 inbias floating v hvin = 76v regout = drvin hvin and inbias input current vs. temperature max5953a/b/c/d toc12 temperature ( c) input current (ma) 100 75 50 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 01 2 5 i inbias i hvin v hvin = v inbias = 76v regout voltage vs. input voltage max5953a/b/c/d toc13 v hin (v) v regout (v) 63 50 37 24 8.76 8.77 8.78 8.79 8.80 8.81 8.82 8.83 8.84 8.858.75 11 76 inbias floating gnd = v ee regout voltage vs. temperature max5953a/b/c/d toc14 temperature ( c) v regout (v) 100 75 50 25 8.72 8.74 8.76 8.78 8.80 8.82 8.84 8.86 8.88 8.908.70 0 125 v hvin = 48v inbias floating regout voltage vs. load current max5953a/b/c/d toc15 i regout (ma) v regout (v) 25 20 15 10 5 8.70 8.75 8.80 8.858.65 03 0 v hvin = 15v inbias floatinggnd = v ee regout voltage vs. input voltage max5953a/b/c/d toc16 v hin (v) v regout (v) 63 50 37 24 10.62 10.64 10.66 10.68 10.7010.60 11 76 hvin = inbiasgnd = v ee regout voltage vs. temperature max5953a/b/c/d toc17 temperature ( c) v regout (v) 100 75 50 25 10.66 10.67 10.68 10.69 10.70 10.71 10.72 10.73 10.74 10.7510.65 01 2 5 v hvin = v inbias = 48v regout voltage vs. load current max5953a/b/c/d toc18 i regout (ma) v regout (v) 25 20 15 10 5 10.55 10.60 10.65 10.70 10.7510.50 03 0 v hvin = v inbias = 15v gnd = v ee downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets _______________________________________________________________________________________ 9 regout uvlo voltage vs. temperature max5953a/b/c/d toc19 temperature ( c) regout uvlo voltage (v) 100 75 50 25 6.2 6.4 6.6 6.8 7.0 7.2 7.46.0 0 125 rising falling operating frequency vs. temperature max5953a/b/c/d toc20 temperature ( c) operating frequency (khz) 100 75 25 50 250 300 350 400 450 500 550 600200 01 2 5 r rtct = 12k ? c rtct = 100pf r rtct = 24.3k ? c rtct = 100pf soft-start current vs. temperature max5953a/b/c/d toc21 temperature ( c) soft-start current ( a) 100 75 50 25 31.5 32.0 32.5 33.0 33.5 34.031.0 0 125 minimum rcff and opto levels vs. temperature max5953a/b/c/d toc22 temperature ( c) v rcff (v), v opto (v) 100 75 50 25 1.25 1.50 1.75 2.00 2.25 2.50 2.751.00 0 125 rcff opto current-limit comparator threshold vs. temperature max5953a/b/c/d toc23 temperature ( c) v regout (v) 100 75 50 25 0.151 0.152 0.153 0.154 0.155 0.156 0.157 0.158 0.159 0.1600.150 01 2 5 hvin rising ppwm to xfrmrl skew vs. temperature max5953a/b/c/d toc24 temperature ( c) ppwm to xfrmrl skew (ns) 100 75 50 25 91 92 93 94 95 96 97 98 99 100 90 01 2 5 fltint current vs. temperature max5953a/b/c/d toc25 temperature ( c) i fltint ( a) 100 75 50 25 76 77 78 79 80 81 82 83 84 8575 0 125 fltint shutdown voltage vs. temperature max5953a/b/c/d toc26 temperature ( c) v fltint (v) 100 75 50 25 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.91.9 01 2 5 rising falling power mosfets r ds(on) vs. temperature max5953a/b/c/d toc27 temperature ( c) r ds(on) ( ? ) 100 75 50 25 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0 125 typical operating characteristics (continued) (v in = (v+ - v ee ) = 48v, gate = pgood = unconnected, gnd connected to out, hvin connected to v+, uvlo = v ee , c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, t j = 0? to +125?, unless otherwise noted. typical values are at t j = +25?. all voltages are referenced to v ee , unless otherwise noted.) downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 10 ______________________________________________________________________________________ pin description pin name function 1, 2, 3, 5, 7, 12, 13, 14, 17, 19, 35, 38, 46, 47, 48 n.c. no connection. not internally connected. make no electrical connection to these pins. 4 v+ positive input power. referenced to v ee . 6 (max5953a/max5953c) uvlo undervoltage lockout programming input for pd interface. uvlo is referenced to v ee . when uvlo is above its threshold, the device enters the power mode. connect uvlo tov ee to use the default undervoltage lockout threshold. connect uvlo to the center of an external resistor-divider between v+ and v ee to define a threshold externally. the series resistance value of the external resistors must add to 25.5k ? (?%) and replaces the detection resistor. to keep the device in undervoltage lockout, drive uvlo betweenv th,g,uvlo and v ref,uvlo . 6 (max5953b/max5953d) n.c. no connection. not internally connected. make no electrical connection to this pin. 8 rclass classification setting for pd interface. rclass is referenced to v ee . add a resistor from rclass to v ee to set a pd class (see tables 1 and 2). 9 gate gate of internal isolation n-channel power mosfet. gate is referenced to v ee . gate sources 10? when the device enters power mode. connect an external 100v ceramiccapacitor from gate to out to program the inrush current. drive gate to v ee to turn off the internal mosfet. the detection and classification functions operate normally whengate is driven to v ee . 10, 11 v ee negative input power. source of the integrated isolation n-channel power mosfet. 15, 16 out output voltage. out is referenced to v ee . out is connected to the drain of the integrated isolation n-channel power mosfet. connect out to gnd. 18 (max5953a/max5953b) pgood active-high, open-drain power-good indicator output for pd interface. pgood isreferenced to out. pgood goes high impedance when v out is within 1.2v of v ee and when v gate is 5v above v ee . otherwise, pgood is internally pulled to out (given that v out is at least 5v below v+). pgood can be connected directly to css or dcuvlo to enable/disable the dc-dc converter. 18 (max5953c/max5953d) pgood active-low, open-drain power-good indicator output for pd interface. pgood is referenced to v ee . pgood is pulled to v ee when v out is within 1.2v of v ee and when v gate is 5v above v ee . otherwise, pgood goes high impedance. 20 cs current-sense input for pwm controller. cs is referenced to pgnd. the current-limitthreshold is internally set to 156mv relative to pgnd. the device has an internal noise filter. if necessary, connect an external rc filter from cs to pgnd for additional filtering. 21 ppwm pwm pulse output. referenced to gnd. ppwm leads the internal power mosfet pulse by approximately 100ns. 22 gnd signal ground of pwm controller. connect gnd to pgnd. 23 pgnd power ground of the dc-dc converter power stage. connect pgnd to gnd. 24 css soft-start timing capacitor connection for pwm controller. css is referenced to gnd.connect a 0.01? or greater ceramic capacitor from css to gnd. connect to pgood to automatically enable the pwm controller from the pd interface. downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 11 pin description (continued) pin name function 25 opto pwm comparator inverting input. opto is referenced to gnd. connect the collector of the optotransistor to opto and a pullup resistor to regout. 26, 27 src source connection of low-side power mosfet in the two-switch power stage of the dc-dc converter. connect src to pgnd with a low-value resistor for current limiting. 28, 29 xfrmrl low-side connection for the isolation transformer. drain terminal of low-side powermosfet in the two-switch power stage of the dc-dc converter. 30 drvin supply input for the gate-driver of internal power mosfets. drvin is referenced topgnd. bypass drvin with at least 0.1? to pgnd. connect drvin to regout. 31, 32 xfrmrh high-side connection for the isolation transformer. source connection of high-side powermosfet in the two-switch power stage of the dc-dc converter. 33, 34 drnh drain connection of high-side mosfet in the two-switch power stage of the dc-dcconverter. connect drnh to the most positive rail of the input supply. bypass drnh appropriately to handle the heavy switching current through the transformer. 36 bst boost input for the dc-dc converter. bst is the boost connection point for the high-sidemosfet driver. connect a minimum 0.1? capacitor from bst to xfrmrh with short and wide pc board traces. 37 dcuvlo dc-dc converter undervoltage lockout input. dcuvlo is referenced to gnd. connect a resistor-divider from hvin to dcuvlo to gnd to set the uvlo threshold. 39 hvin dc-dc converter positive input power supply. hvin is referenced to gnd. connect hvinto v+. 40 inbias input from the rectified bias winding to the dc-dc converter. inbias is referenced tognd. inbias is the input to the internal linear voltage regulator (regout). 41 regout internal regulator output. regout is used for the dc-dc converter gate driver. regoutis referenced to gnd. v regout is always present as long as hvin is powered with a voltage above the dcuvlo threshold. bypass regout to gnd with a minimum 2.2?ceramic capacitor. 42 rtct oscillator frequency set input for the pwm controller. rtct is referenced to gnd.connect a resistor from rtct to regout and a ceramic capacitor from rtct to gnd to set the oscillator frequency. 43 fltint fault integration input for pwm controller. fltint is referenced to gnd. during persistentcurrent-limit faults, a capacitor connected to fltint is charged with an internal 80? current source. switching is terminated when v fltint reaches 2.7v. an external resistor connected in parallel discharges the capacitor. switching resumes when v fltint drops to 1.9v. 44 rcff feed-forward input for pwm controller. rcff is referenced to gnd. to generate the pwmramp, connect a resistor from rcff to hvin and a capacitor from rcff to gnd. 45 ramp ramp sense input for pwm controller. connect ramp to rcff. ? p exposed paddle. ep is internally unconnected and must be connected to v ee externally. to improve power dissipation, solder the exposed paddle to a copper pad on the pcboard. downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 12 ______________________________________________________________________________________ typical application circuit phy -48v -48v rtn tx rx sgnd rj-45 power-over spair pairs 36 12 45 7 8 power-over signal pairs + - + - v reg figure 2. rj-45 connector, poe magnetic, and input diode bridges downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 13 pgood v+uvlo r1*open r3 (r disc ) 25.5k ? c2 22 f 63v r5 200k ? c3 220pf c4 4.7 f c5 6800pf r6 24.9k ? r7 1.78k ? *r1 and r2 are optional and when used, they must total 25.5k ? and replace r3, 25.5k ? . c1 68nf d1 60v -48v rtn -48v r2*open r4 (r rclass ) 255 ? 46 8 rclass 18 dcuvlo 37 r16 316k ? r17 14.7k ? hvin 39 drnh ppwm bst c110.1 f d2 d3 c12a 47 f 33, 34 21 36 xfrmrh 31, 32 xfrmrl 28, 29 inbias 40 r13 15 ? d6 v ee 10 rcff 44 ramp 45 drvin 30 gate 9 out 16 regout fltint 43 42 24 rtct css 22 gnd 25 opto 41 c6 0.1 f c7100pf r91m ? c80.1 f 23 pgnd pgnd e u2 fod2712 c led fb gnd comp 20 cs 26, 27 src c9 220pf r10 100 ? r110.1 ? r8open c10 0.33 f r12 604 ? r16562 ? c16 0.15 f c17 0.047 f r1516.2k ? r14143k ? d4 22t 25t 11t c151 f c12b47 f c130.1 f out sgnd c140.0047 f max5953a figure 3. typical application circuit downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 14 ______________________________________________________________________________________ pgood v+uvlo r1* r3 (r disc ) 25.5k ? c1 68nf d1 60v -48v rtn -48v r2* r rclass 46 8 rclass 18 dcuvlo 37 hvin 39 drnh ppwm bst 33, 34 21 36 xfrmrh 31, 32 xfrmrl 28, 29 inbias 40 v ee 10 rcff 44 ramp 45 drvin 30 gate 9 out 16 regout fltint 43 42 24 rtct css 22 gnd 25 opto 41 23 pgnd pgnd e u2 fod2712 c led fb gnd comp 20 cs 26, 27 src v out sgnd max5953a *r1 and r2 are optional and when used, they must total 25.5k ? and replace r3, 25.5k ? . figure 4. for higher power applications, the max5953a/max5953b/max5953c/max5953d can be used in a two-switch forward converter configuration downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 15 detailed description pd interface the max5953a/max5953b/max5953c/max5953dinclude complete interface function for a pd to comply with the ieee 802.3af standard in a poe system. they provide the pd with a detection signature, a classifica- tion signature, and an integrated isolation switch with programmable inrush current control. an integrated mosfet provides pd isolation during detection and classification. all devices guarantee a leakage current offset of less than 10? during the detection phase. a programmable current limit prevents high inrush cur- rent during power-on. the device features power-mode uvlo with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to assure glitch-free transition between detection, classifi- cation, and power-on/-off phases. the max5953a/ max5953c have an adjustable uvlo threshold with the default value compliant to the 802.3af standard, while the max5953b/max5953d have a lower and fixed uvlo threshold compatible with some legacy pre-802.3af pse. operating modes depending on the input voltage (v in = v + - v ee ), the pd front-end section of the max5953a/max5953b/max5953c/max5953d operate in three different modes: pd detection signature, pd classification, and pd power. all voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the ieee 802.3af standard (see figure 2). detection mode (1.4v v in 10.1v) in detection mode, the power source equipment (pse)applies two voltages on v in in the range of 1.4v to 10.1v (1v step minimum), and records the corresponding cur- rent measurements at those two points. the pse then computes ? v/ ? i to ensure the presence of the 25.5k ? signature resistor. in this mode, most interface circuitryof the max5953a/max5953b/max5953c/max5953d is off and the offset current is less than 10?. classification mode (12.6v v in 20v) in the classification mode, the pse classifies the pdbased on the power consumption required by the pd. this allows the pse to efficiently manage power distrib- ution. the ieee 802.3af standard defines five different classes as shown in table 1. an external resistor (r rclass ) connected from rclass to v ee sets the classification current.the pse determines the class of a pd by applying a voltage at the pd input and measuring the current sourced out of the pse. when the pse applies a volt- age between 12.6v and 20v, the ic exhibits a current characteristic with values indicated in table 2. the pse uses the classification current information to classify the power requirement of the pd. the classification cur- rent includes the current drawn by the 25.5k ? detec- tion signature resistor and the supply current of the icso the total current drawn by the pd is within the ieee 802.3af standard figures. the classification current is turned off whenever the device is in power mode. table 1. pd power classification/r rclass selection table 2. setting classification current * class 4 reserved for future use. * v in is measured across the max5953a/max5953b/max5953c/max5953d input pins (v+ - v ee ), which do not include the diode bridge voltage drop. class usage r rclass ( ? ) maximum power used by pd (w) 0 default 10k 0.44 to 12.95 1 optional 732 0.44 to 3.84 2 optional 392 3.84 to 6.49 3 optional 255 6.49 to 12.95 4 not allowed 178 reserved* class current seen at v in (ma) ieee 802.3af pd classification current specification (ma) class r rclass ( ? ) v in * (v) min max min max 0 10k 12.6 to 20 0 2.00 0 4 1 732 12.6 to 20 9.17 11.83 9 12 2 392 12.6 to 20 17.29 19.71 17 20 3 255 12.6 to 20 26.45 29.55 26 30 4 178 12.6 to 20 36.60 41.40 36 44 downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 16 ______________________________________________________________________________________ power mode during power mode, when v in rises above the undervolt- age lockout threshold (v uvlo,on ), the ic gradually turns on the internal n-channel mosfet q1 (see figure 8). the ic charges the gate of q1 with a constant current source (10?, typ). the drain-to-gate capacitance of q1 limits the voltage rise rate at the drain of the mosfet, thereby limiting the inrush current. to further reduce the inrush current, add external drain-to-gate capacitance (see the inrush current limit section). when the drain of q1 is within 1.2v of its source voltage and its gate-to-source voltage is above 5v, the max5953a/max5953b assert the pgood output (max5953c/max5953d assert the pgood output). the ic has a wide uvlo hysteresis and turn-off deglitch time to compensate for the highimpedance of the twisted-pair cable. undervoltage lockout for pd interface the ic operates up to a 67v supply voltage with a defaultuvlo turn-on (v uvlo,on ) set at 38.6v (max5953a/ max5953c) or 35.4v (max5953b/max5953d) and auvlo turn-off (v uvlo,off ) set at 30v. the max5953a/ max5953c have an adjustable uvlo threshold using a resistor-divider connected to uvlo (see figure 3). when the input voltage goes below the uvlo threshold for more than t off_dly , the mosfet turns off. to adjust the uvlo threshold, connect an externalresistor-divider from v+ to uvlo to v ee . use the follow- ing equations to calculate r1 and r2 for a desireduvlo threshold: where v in,ex is the desired uvlo threshold. since the resistor-divider replaces the 25.5k ? pd detection resis- tor, ensure that the sum of r1 and r2 equals 25.5k ? ?%. when using the external resistor-divider, max5953a/max5953c have an external reference voltage hysteresis of 20% (typ). in other words, when uvlo is programmed externally, the turn-off threshold is 80% (typ) of the new uvlo threshold. inrush current limit the ic charges the gate of the internal mosfet with aconstant current source (10?, typ). the drain-to-gate capacitance of the mosfet limits the voltage rise rate at the drain, thereby limiting the inrush current. add an external capacitor from gate to out to further reduce the inrush current. use the following equation to calcu- late the inrush current: the recommended typical inrush current for a poeapplication is 100ma. pgood/ pgood output pgood is an open-drain, active-high logic output.pgood goes high impedance when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood is pulled to v out (given that v out is at least 5v below v+). connect pgood directly tocss to enable/disable the dc-dc converter. pgood is an open-drain, active-low logic output. pgood is pulled to v ee when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood goes high impedance. connect a 100k ? pullup resistor from pgood to v+ if needed. thermal dissipation thermal shutdown limits total power dissipation in the ic. if the junction temperature exceeds +160?, ther- mal shutdown is enabled to turn off the max5953a/ max5953b/max5953c/max5953d, allowing the ic to cool. the ic turns on after the junction temperature cools by 20?. dc-dc converter the max5953a/max5953b/max5953c/max5953d iso-lated pwm power ics feature integrated switching power mosfets connected in a voltage-clamped, two-transis- tor, power-circuit configuration. these devices can be used in both forward and flyback configurations with a wide 11v to 76v input voltage range. the voltage- clamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. a look-ahead signal for driving secondary-side synchronous rectifiers can be used to increase efficiency. a wide array of protection features include uvlo, overtemperature shutdown, and short-cir- cuit protection with hiccup current-limit for enhanced performance and reliability. operation up to 500khz allows smaller external magnetics and capacitors. power topology the two-switch forward-converter topology offers out-standing robustness against faults and transformer sat- uration while affording efficient use of 0.4 ? power mosfets. voltage-mode control with feed-forwardcompensation allows the rejection of input supply dis- turbances within a single cycle similar to that of current- mode controlled topologies. ii c c inrush g out gate = rk v v rk r ref uvlo in ex 2255 1255 2 = = . . , , ? ? downloaded from: http:///
the two-switch power topology recovers energy stored in both the magnetizing and the parasitic leakage induc- tances of the transformer. the typical application circuit , figure 3, shows the schematic diagram of a -48v input flyback converter using the max5953a. figure 4 shows the schematic diagram of a -48v input forward converter and a 5v, 3a output isolated power supply. voltage-mode control and the pwm ramp for voltage-mode control, the feed-forward pwm rampis generated at rcff. from rcff, connect a capacitor to gnd and a resistor to hvin. the ramp generated is applied to the noninverting input of the pwm compara- tor at ramp and has a minimum voltage of approxi- mately 2v. the slope of the ramp is determined by the voltage at hvin and affects the overall loop gain. the ramp peak must remain below the 5.5v dynamic range of rcff. assuming the maximum duty cycle approach- es 50% at a minimum input voltage (pwm uvlo turn- on threshold), use the following formula to calculate the minimum value of either the ramp capacitor or resistor: where f s is the switching frequency, v r(p-p) is the peak- to-peak ramp voltage (2v, typ). select r rcff resistance value between 200k ? and 600k ? . maximize the signal-to-noise ratio by setting the ramppeak as high as possible. calculate the low-frequency, small-signal gain of the power stage (the gain from the inverting input of the pwm comparator to the output) using the following formula: g ps = n sp x r rcff x c rcff x f s where n sp is the secondary to primary power trans- former turns ratio. secondary-side synchronization the max5953a/max5953b/max5953c/max5953d provide convenient synchronization for optional sec- ondary-side synchronous rectifiers. figure 5 shows the connection diagram with a high-speed optocoupler. choose an optocoupler with a propagation delay of less than 80ns. the synchronizing pulse is generated approximately 110ns ahead of the main pulse that dri- ves the two power mosfets. undervoltage lockout for dc-dc converter connect pgood to dcuvlo to ensure the pd interfaceis ready prior to the dc-dc converter. the dcuvlo block monitors the input voltage at hvin through an external resistive divider (r16 and r17) connected to dcuvlo (see figure 3). use the following equation to calculate r16 and r17: where v dcuvloin is the desired input voltage lockout level and v dcuvlo is the undervoltage lockout thresh- old (1.25v, typ). select the r17 resistance valuebetween 100k ? and 500k ? . optocoupled feedback isolated voltage feedback is achieved by using an optocoupler as shown in figure 3. connect the collec- tor of the optotransistor to opto and a pullup resistor between opto and regout. internal regulators as soon as power is provided to hvin, internal powersupplies power the dcuvlo detection circuitry. regout is used to drive the internal power mosfets. bypass regout to gnd with a minimum 2.2? ceram- ic capacitor. the hvin ldo steps down v hvin to a nominal output voltage (v regout ) of 8.75v. a second parallel ldo powers regout from inbias. a tertiarywinding connected through a diode to inbias powers up regout once switching commences. this powers regout to 10.5v (typ) and shuts off the current flow- ing from hvin to regout. this results in a lower on- chip power dissipation and higher efficiency. vv rr dcuvloin dcuvlo = + ?? ? ?? ? 1 1617 rc v fv rcff rcff in ex srpp , () 2 max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 17 c +5v r max5953amax5953b max5953cmax5953d ppwm pgnd figure 5. secondary-side synchronous rectifier driver using ahigh-speed optocoupler downloaded from: http:///
max5953a/max5953b/max5953c/max5953d soft-start program the max5953a/max5953b/max5953c/max5953d soft-start with an external capacitor (c css ) connected between css and gnd. when the deviceturns on, c css charges with a constant current of 33?, ramping up to 7.3v. during this time, the feed- back input (opto) is clamped to v css + 0.6v. this ini- tially holds the duty cycle lower than the value theregulator imposes, thus preventing voltage overshoot at the output. when the ic turns off, the soft-start capaci- tor internally discharges to gnd. oscillator the oscillator is externally programmable through aresistor connected from rtct to regout and a capacitor connected from rtct to gnd. the pwm fre- quency is one-half the frequency seen at rtct with a 50% duty cycle. use the following formula to calculate the oscillator components: where c pcb is the stray capacitance on the pc board (14pf, typ), v th,rtct is the rtct peak trip level, and f s is the switching frequency. integrating fault protection the integrating fault protection feature allows the ic to ignore transient overcurrent conditions for a program- mable amount of time, giving the power-supply time to behave like a current source to the load. this can hap- pen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. the ignore time is programmed externally by connecting a capaci- tor from fltint to gnd. under sustained overcurrent faults, the voltage across this capacitor ramps up toward the fltint shutdown threshold (2.7v, typ). when v fltint reaches the shutdown threshold, the power supply shuts down. a high-value bleed resistorconnected in parallel with the fltint capacitor allows the capacitor to discharge toward the restart threshold (1.9v, typ). fltint drops to the restart threshold allow- ing for soft-starting the supply again. the fault integration circuit works by forcing an 80? current into fltint for one clock cycle every time the current-limit comparator ilim (figure 9) trips. use the following formula to calculate the approximate capaci- tor needed for the desired shutdown time: where i fltint is typically 80?, and t sh is the desired ignore time during which current-limit events from thecurrent-limit comparator are ignored. this is an approximate formula; some testing may be required to fine tune the actual value of the capacitor. calculate the approximate bleed resistor needed for the desired recovery time using the following formula: where t rt is the desired recovery time. choose t rt 10 x t sh . typical values for t sh can range from a few hundred microseconds to a few milliseconds. shutdown shut down the controller section of the ic by drivingdcuvlo to gnd using an open-collector or open-drain transistor connected to gnd. the dc-dc converter sec- tion shuts down if regout is below its dcuvlo level. current-sense comparator the current-sense (cs) comparator and its associatedlogic limit the peak current through the internal mosfet. current is sensed at cs as a voltage across a sense resistor between the source of the mosfet and gnd.the power mosfet switches off when the voltage at cs reaches 156mv. select the current-sense resistor, r sense , according to the following equation: r sense = 0.156v / i limprimary where i limprimary is the maximum peak primary-side current.to reduce switching noise, connect cs to an external rc lowpass filter for additional filtering (figure 3). applications information design example design example 1: pd with three-output flyback dc-dc converter figure 6 shows an isolated three-output flyback dc-dc converter. it provides output voltages of 10v at 30ma, 5.1v at 1.8a, and 2.55v at 5.4a. design example 2: pd with nonisolated step-down (buck) converter figure 7 shows a buck converter with 12v, 0.75a out- put. caution: this converter does not have active cur- rent limit. r t c fltint rt fltint ? 0 3514 . c it fltint fltint sh ? 14 . r fc c in v vv rtct s rtct pcb regout regout th rtct ? + () ?? ? ?? ? 1 2 , ieee 802.3af pd interface and pwm controllers with integrated power mosfets 18 ______________________________________________________________________________________ downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 19 pgood v+uvlo r1*open r3 (r disc ) 25.5k ? c10 22 f 63v r5210k ? c2 100pf c3 2.2 f c4 4700pf r7 25.5k ? r11 2k ? *r1 and r2 are optional and when used, they must total 25.5k ? and replace r3, 25.5k ? . c1 0.068 f d1 56.7v -48v rtn -48v inbias r2*0 ? r4 (r cl ) 255 ? 46 8 rclass 18 dcuvlo 37 r16 316k ? r17 14.7k ? hvin 39 drnh ppwm ppwm bst c90.22 f d11 t1 d3 d2 d10 r6 100 ? c24 0.1 f r2810k ? -48v out t2 pa0264 ppwm g1 d12 r16 1k ? r17 22 ? g2 n4 33, 34 21 36 xfrmrh 31, 32 xfrmrl 28, 29 inbias 40 d6 v ee 10 rcff 44 ramp 45 drvin 30 gate 9 out 16 regout fltint 43 42 24 rtct css 22 gnd 25 opto 41 c5 1000pf c6100pf r81m ? c70.01 f 23 pgnd e 32 8 76 5 u2 fod2712 c led fb gnd comp 20 cs 26, 27 src c8 100pf r9 1k ? r100.18 ? c13 0.22 f r14 470 ? r22221 ? c19 0.068 f c20 0.068 f c210.1 f r212.52k ? r202.74k ? c120.1 f v out1 (10v at 30ma) max5953a u1 r6210k ? gate -48v out r15 210k ? r25 open n.c. 1, 4 r241k ? r23 1m ? d8 d5 v out2 c22220 f c23220 f a1 d7 v out3 a2 inbias c110.1 f n3 a2 v out2 rtn d4 r18 22 ? r191k ? g1 n2 n1 a1 -48v out v out3 v out2 (5.1v at 1.8a) v out3 (2.55v at 5.4a) c17a 100 f c16 100pf c140.47 f c17220 f c182200pf c1522 f c25 0.1 f a1 d9 r2710k ? g2 c26 0.1 f a2 figure 6. pd with three-output flyback dc-dc converter downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 20 ______________________________________________________________________________________ pgood pgood u1 r9 14.7k ? r8 316k ? v+ r1 (r disc ) 25.5k ? c2 22 f 63v c1 68nf r3 210k ? c3 100pf c6 150pf c7100pf c80.022 f pgood d1 60v -48v rtn -48v 0.5a r2 (r rclass ) 255 ? c5 4700pf c4 2.2 f r4 26.7k ? r6100k ? r5 1k ? 48 rclass 18 dcuvlo 37 hvin 39 drnh ppwm bst 33, 34 21 36 xfrmrh 31, 32 xfrmrl 28, 29 inbias 40 d4 v ee 10 rcff 44 ramp 45 drvin 30 gate 9 out 16 regout fltint 43 42 24 rtct css 22 gnd 25 opto 41 23 pgnd pgnd c9open c131 f r10open r1314.3k ? r116.81k ? r121.78k ? r7 3.9k ? l1 220 h c100.022 f c160.01 f c140.15 f c1122 f c121 f 20 cs 26, 27 tl431cd src r164.99k ? c150.03 f out 12v, 0.75a gnd max5953a figure 7. pd with nonisolated step-down (buck) converter downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 21 layout recommendations all connections carrying pulsed currents must be veryshort, as wide as possible, and have a ground plane as a return path. the inductance of these connections must be kept to a minimum due to the high di/dt of the currents in high-frequency-switching power converters. current loops must be analyzed in any layout pro-posed, and the internal area kept to a minimum to reduce radiated emi. ground planes must be kept as intact as possible. table 3. component suppliers component suppliers website international rectifier www.irf.com fairchild www.fairchildsemi.com power fets vishay-siliconix www.vishay.com/brands/siliconix/main.html dale-vishay www.vishay.com/brands/dale/main.html current-sense resistors irc www.irctt.com/pages/index.cfm on semi www.onsemi.com general semiconductor www.gensemi.com diodes central semiconductor www.centralsemi.com sanyo www.sanyo.com taiyo yuden www.t-yuden.com capacitors avx www.avxcorp.com coiltronics www.cooperet.com coilcraft www.coilcraft.com magnetics pulse engineering www.pulseeng.com downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 22 ______________________________________________________________________________________ block diagrams v+ uvlo v+ uvlo* *max5953a/max5953c only. **max5953c/max5953d only. ***max5953a/max5953b only. gate max5953amax5953b max5953cmax5953d classification rclass pgood** 6.8v en ref 2.4v ref 2.4v, 0.8 hyst 21.8v 39v 200mv v ee v gate , 6v 1.2v, ref 5v, ref q4 pgood*** out q3 q10.6 ? q238 ? en figure 8. powered device interface block diagram downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 23 figure 9. dc-dc converter block diagram (voltage-mode pwm controller and two-switch power stage) ovtdcuvlo refok regok ovrld t t 5v 5v 80 a 33 a iflt 5v ovrld cpwm ilim dcuvlo regoutrcff fltintramp optocss gnd inbias hvin dcuvlo ppwm bst xfrmrh drvin xfrmrl drnh src pgnd rtct cs regok reg ovt refok ref (1.25v) 7.5v 50 ? gnd q d r q r t-ff shdn osc 50 ? gnd rs q clk thermal shutdown ovt 1.25v dcuvlo 80ns delay leading- edge delay one shot level shift 10mhz pgnd 150mv qh qb ql 0.4 ? 30 ? 0.4 ? max5953amax5953b max5953cmax5953d 2.7v/1.9v block diagrams (continued) downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 24 ______________________________________________________________________________________ typical operating circuit pgood v+uvlo r1* r3 (r disc ) 25.5k ? c1 68nf d1 60v -48v rtn -48v r2* r rclass 46 8 rclass 18 dcuvlo 37 hvin 39 drnh ppwm bst 33, 34 21 36 xfrmrh 31, 32 xfrmrl 28, 29 inbias 40 v ee 10 rcff 44 ramp 45 drvin 30 gate 9 out 16 regout fltint 43 42 24 rtct css 22 gnd 25 opto 41 23 pgnd pgnd e u2 fod2712 c led fb gnd comp 20 cs 26, 27 src out sgnd max5953a u1 *r1 and r2 are optional and when used, they must total 25.5k ? and replace r3, 25.5k ? . downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets ______________________________________________________________________________________ 25 chip information process: bicmos selector guide pin configuration part pgood or pgood uvlo max5953a pgood adjustable max5953b pgood fixed max5953c pgood adjustable max5953d pgood fixed top view max5953amax5953b max5953cmax5953d thin qfn 7mm x 7mm 13 14 15 16 17 18 19 20 21 22 23 24 n.c. n.c. out out n.c. ** n.c. cs ppwm gnd pgnd css 48 47 46 45 44 43 42 41 40 39 38 37 1 2 345678910 11 12 n.c. n.c. n.c. ramp rcff fltint rtct regout inbias hvin n.c. dcuvlo *uvlo for max5953a/max5953c n.c. for max5953b/max5953d ** pgood for max5953a/max5953b pgood for max5953c/max5953d + n.c. v ee v ee gate rclass n.c. * n.c. v+ n.c. n.c. n.c. 36 35 34 33 32 31 30 29 28 27 26 25 opto src src xfrmrl xfrmrl drvin xfrmrh xfrmrh drnh drnh n.c. bst downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets 26 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k detail b e l l1 package outline 21-0144 2 1 e 32, 44, 48, 56l thin qfn, 7x7x0.8m m downloaded from: http:///
max5953a/max5953b/max5953c/max5953d ieee 802.3af pd interface and pwm controllers with integrated power mosfets maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. m. quijano package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) package outline 21-0144 2 2 e 32, 44, 48, 56l thin qfn, 7x7x0.8m m revision history pages changed at rev 1: 1, 27 downloaded from: http:///

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